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IGNOU MCS-202 (January 2026 – July 2026) Assignment Questions
Question 1:
(a) Explain the von Neumann architecture with the help of a diagram. Also, explain how the data and instructions are stored in this architecture.
(b) Explain how a computer will execute the following high-level language program segment:
int x=10, y=20, result;
result=x+y;
(c) Perform the following conversion of numbers:
(i) Decimal (1479865320)10 to binary and hexadecimal.
(ii) Hexadecimal (BCDAFD01)h to binary and Octal.
(iii) ASCII String “BCA Programme Code is BCA_NEW & BCA_NEWOL” to UTF-8
(iv) Octal (72143065)O to Decimal
(d) Simplify the following function using a K-map: F(A, B, C, D) = Σ (1,3, 4, 5, 7, 11, 12). Draw the circuit for the simplified function using NAND gates.
(e) Consider the Adder-Subtractor circuit given in Unit 3 of Block 1. Explain how this circuit will perform subtraction (A-B) if the value of A is 1001 and B is 0111. You must list all the bit values, including Cin, Cout, and the overflow condition.
(f) Make the Truth Table and draw the logic diagram of a 3×8 decoder. Explain its functioning with the help of a truth table and an example input.
(g) Assume that a source data value 1011 was received at a destination as 0011. Show how Hamming’s Error-Correcting code will be appended to the source data, so this one-bit error is identified and corrected at the destination. You may assume that the transmission error occurs in the source data and not in the error correction code.
(h) Explain the functioning of the RS flip-flop with the help of a logic diagram and a characteristic table. Also, make and explain the excitation table of this flip-flop.
(i) Explain the functioning of a synchronous counter.
(j) Represent (-729.25)10 and (0.0078125)10 in IEEE 754 single precision format.
Question 2:
(a) (i) Explain the structure of a 4x2ROM with the help of a diagram.
(ii) How many memory chips of size 128K x8bits are needed to build a RAM of size 64 M words if the word size of RAM is 32 bits?
(iii) Find the storage capacity of a Magnetic disk with 16 recording surfaces, and 256 tracks consisting of 256 sectors each. You may assume that each sector can store 1 MB of data. (iv) Find the rotational latency of a disk that rotates at 9000 rpm.
(b) Consider that the main memory of a computer is 256 words (assume a memory word to be 32 bits). The cache memory of this computer consists of 8 blocks, each 128 bits in size. Find the cache addresses for the main memory addresses 011000112 and 110101112 for the following cache mapping schemes:
(i) Associative cache mapping
(ii) Direct cache mapping
(iii) Two-way set associative cache mapping
(c) Explain the steps of a Direct Memory Access (DMA) transfer. What are the advantages of using the DMA technique of data transfer? Illustrate the DMA breakpoints in an instruction cycle with the help of a diagram.
(d) What is an interrupt? Explain the steps of interrupt processing with the help of a diagram. Explain the design issues for implementing interrupt-driven Input/Output (I/O).
(e) Explain the features of the following I/O Technologies:
(i) Active-Matrix Liquid Crystal Displays
(ii) Colour Depth in the context of Video cards
(iii) Scanners
(iv) Non-impact printers
Question 3:
(a) Explain the functioning of subroutine call and return instructions with the help of an example. Also, explain indirect addressing, indexed addressing, and stack addressing with the help of an example for each.
(b) Demonstrate how the size of a machine program changes for the computation of the expression result=(a+b) * (a*b+c) when the instruction sets have (i) zero address instructions, (ii) one address instructions, (iii) two address instructions, and (iv) three address instructions.
(c) Consider a machine that uses PC, IR, AC, and MAR registers to execute different instructions. All the memory accesses during instruction execution bring data to a temporary register named TR. The ALU of the machine performs the subtraction operation using the AC and TR registers, and the result of the subtraction operation is stored in the AC register. List and explain all the microoperations required to execute the following machine instruction:
AC ← AC -M; where M is the address of a direct operand in the Memory Assume that PC is currently pointing to this instruction. Make and state suitable assumptions, if any.
(d) Explain the operation of a micro-programmed control unit with the help of a diagram.
(e) What are the features of a RISC machine? Explain the RISC pipelining with the help of a diagram.
Question 4:
(a) What is a Flag register in the 8086 microprocessor? Explain any four flags and their use. What is the need for a segment register in the 8086 microprocessor? Compute the physical address for the following {Segment Register : Offset} pairs in an 8086 microprocessor:
(i) CS: IP = ABCDh:AAFFh
(ii) DS:BX = 1FBHh:99FFh
(iii) SS: SP = EFFFh: 00ABh
(b) What is an Interrupt Vector Table (IVT) in the 8086 microprocessor? Explain its use with the help of a diagram. Write a program using 8086 assembly language to input a string: “Welcome to the Programme.”
(c) Write a program in 8086 assembly language that converts a 4-bit unsigned binary number to an equivalent unpacked BCD value. For example, the input binary number 11012 is first converted to its equivalent BCD value, 13, i.e., 000100112. This value is then unpacked and stored as unpacked BCD values, 000000012 and 000000112. Explain the algorithm of the program.
(d) Explain the features and advantages of the following:
(i) Pipeline for adding two floating-point numbers
(ii) Vector Processing
(iii) Bus interconnection structure in a multiprocessor system
(iv) Multi-core processors
(v) Inter-processor communication and synchronisation
IGNOU MCS-202 (January 2025 – July 2025) Assignment Questions
Question 1: (a) Explain the Harvard architecture with the help of a diagram.Explain how the data and instructions will be stored in Harvard Architecture.
(b) Explain how a computer will execute the following high-level language program segment:
int a=25, b=75, c;
c=b-a;
(c) Perform the following conversion of numbers:
(i) Decimal (9567438120)10 to binary and hexadecimal.
(ii) Hexadecimal (8FAEB1DC)h to binary and Octal.
(iii) ASCII String “ABCabc$#4325 & Unicode” to UTF 8
(iv) Octal (41302576)O to Decimal
(d) Simplify the following function using K-map: F(A, B, C, D) = Σ (1, 3, 5, 7, 8, 12, 14, 15). Draw the circuit of the simplified function using NAND gates.
(e) Consider the Adder-Subtractor circuit given in Unit 3 of Block 1. Explain how this circuit will perform subtraction (A-B) if the value of A is 0011 and B is 1101. You must list all the bit values, including Cin and Cout and overflow condition.
(f) Make the Truth Table and draw the logic diagram of a 4×1 multiplexer. Explain its functioning with the help of an example input.
(g) Assume that a source data value 1111 was received at a destination as 0111. Show how Hamming’s Error-Correcting code will be appended to the source data, so this one-bit error is identified and corrected at the destination. You may assume that the transmission error occurs in the source data and not in the error correction code.
(h) Explain the functioning of the JKflip-flop with the help of a logic diagram and characteristic table. Also, make and explain the excitation table of this flip-flop.
(i) Explain the functioning of a master-slave flip-flop with the help of a diagram.
(j) Represent (-126.5)10 and (0.015625)10 in IEEE 754 single precision format.
Question 2: (a) (i) Explain the structure of a 16 x4 ROM with the help of a diagram. (ii) How many memory chips of size 64K 4 bits are needed to build a RAM of size 32 M words if the word size of RAM is16 bits?(iii) Find the storage capacity of a Magnetic disk with 8 recording surfaces, and 128 tracks consisting of128 sectors each. You may assume that each sector can store 512KB of data. (iv) Find the rotational latency of a disk that rotates at 3000 rpm.
(b) Consider that the main memory of a computer is 128 words (assume a memory word to be 16 bits). The cache memory of this computer has 8 blocks of size 32 bits each. Find the cache addresses for the main memory addresses 01110012 and10101012 if the following cache mapping schemes is used:
(i) Associative cache mapping
(ii) Direct cache mapping
(iii) Two-way set associative cache mapping
(c) What is the DMA technique of data transfer? Why is DMA needed? Explain the DMA breakpoints in an instruction cycle with the help of a diagram. Also, explain any one DMA configuration.
(d) Explain the Programmed I/O and Interrupt driven I/O techniques with the help of a diagram of each. How are these two techniques different from each other? Also, explain the steps of interrupt processing.
(e) Explain the features of the following I/O Technologies:
(i) Bit-mapped Graphics Image and Frame Buffer
(ii) Refresh Rate of Video controllers
(iii) Impact printers
(iv) Voice-based Input devices
Question 3: (a) Explain the functioning of Branch, Jump and Bit manipulation instructions with the help of an example/diagram of each. Also, explain the following addressing modes with the help of an example–Relative Addressing Scheme and Base register addressing scheme.
(b) Demonstrate how the size of a machine program changes for the computation of the expression a=(x*y) + (x*y+z) when different instruction sets, having zero address, one address, two address and three address instructions, are used.
(c) Consider a machine that uses PC, IR, AC, and MAR registers to execute different instructions. All the memory accesses during instruction execution bring data to a register named XR. ALU of the machine performs the addition operation using AC and XR registers, and results are stored in the AC register. List and explain all the microoperations required to execute the following machine instruction:
AC ← AC + X; where X is the address of a direct operand in the Memory
Assume that PC is currently pointing to this instruction. Make and state suitable assumptions, if any.
(d) Explain the Wilkes Control unit with the help of a diagram. Also, explain different microinstruction formats with the help of diagrams.
(e) Explain the use of large register file in RISC processor. Also, explain the circular buffer organisation of overlapped register windows in RISC with the help of a diagram.
Question 4: (a) What are the different types of Registers used in the 8086 microprocessor? Explain the use of each type of register of the 8086 microprocessor. Compute the physical address for the following<segment register:offset> pairs in an 8086 microprocessor:
(i) CS: IP = 12FBh: 567Dh
(ii) DS:BX = 99AEh: 7551h
(iii) SS: SP = 3241h:77FFh
(b) How does the 8086 microprocessor process interrupt? Explain with the help of a diagram. Write a program using 8086 assembly language to output a string: “Present Year is 2025.”
(c) Write a program in 8086 assembly language, which converts an input of 4 ASCII digits to an equivalent hexadecimal number. For example, an input string of 4 ASCII digits, say “4”, “5”, “3”, “2,” will be converted to the hexadecimal equivalent of number 4532, which is 11B4h. Explain the algorithm of the program.
(d) List the characteristics of the following:
(i) Arithmetic Pipeline
(ii) Instruction Pipeline
(iii) SIMD array processor
(iv) Interconnection Structures of Multiprocessors
(v) Cache Coherence
